Cypress - CY7C1246V18

Below are all the different types of Cypress. Select the device of your choice, to download the manual

Contents

CY7C1246V18 CY7C1257V18 CYPRESS _ CY7C1248V18 CY7C1250V18 36 Mbit DDR II h SRAM 2 Word Burst Architecture 2 0 Cycle Read Latency Features 36 Mbit density 4M x 8 4M x 9 2M x 18 1M x 36 300 MHz to 375 MHz clock for high bandwidth 2 Word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 750 MHz at 375 MHz Read latency of 2 0 clock cycles Two Input clocks K and K for precise DDR timing SRAM uses rising edges only Echo clocks CQ and CQ simplify data capture In high speed systems Data valid pin QVLD to indicate valid data on the output Synchronous internally self timed writes Core Vdd 1 8V 0 1V 10 Vddq 1 4V to Vdd I HSTL inputs and variable d ...