Xilinx - XAPP721

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Application Note Virtex 4 Series 1 XILINX High Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES XAPP721 vl 3 February 2 2006 Author Maria George Summary This application note describes a data capture technique for a high performance DDR2 SDRAM interface This technique uses the Input Serializer Deserializer ISERDES and Output Serializer Deserializer OSERDES features available in every Virtex 4 I O This technique can be used for memory interfaces with frequencies of 267 MHz 533 Mb s and above Introduction A DDR2 SDRAM interface is source synchronous where the read data and read strobe are transmitted edge aligned To capture this transmitted data using Virtex 4 FPGAs either the strobe or the data can be delayed In thi ...