Cypress - CY7C1177V18

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Contents

CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 CYPRESS PERFORM 18 Mbit DDR II SRAM 2 Word Burst Architecture 2 5 Cycle Read Latency Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz to 400 MHz ciock for high bandwidth 2 Word burst for reducing address bus frequency Doubie Data Rate DDR interfaces data transferred at 800 MHz at 400 MHz Read iatency of 2 5 ciock cycies Two input ciocks K and K for precise DDR timing SRAM uses rising edges oniy Echo ciocks CQ and CQ simpiify data capture in high speed systems Data vaiid pin QVLD to indicate vaiid data on the output Synchronous internaiiy seif timed writes Core Vdd 1 8V 0 1V 10 Vddq 1 4V to Vdd I HSTL inputs a ...