Cypress - CY7C2565KV18

Below are all the different types of Cypress. Select the device of your choice, to download the manual

Contents

CY7C2561KV18 CY7C2576KV18 W0 CYPRESS PRELIMINARY CY7C2563KV18 CY7C2565KV18 72 Mbit QDR II SRAM 4 Word Burst Architecture 2 5 Cycle Read Latency with ODT Features Separate independent read and write data ports Supports concurrent transactions 550 MHz clock for high bandwidth 4 word burst for reducing address bus frequency Double Data Rate DDR interfaces on both read and write ports data transferred at 1100 MHz at 550 MHz Available in 2 5 clock cycle latency Two input clocks K and K for precise DDR timing SRAM uses rising edges only Echo clocks CQ and CQ simplify data capture in high speed systems Data valid pin QVLD to indicate valid data on the output On Die Termination ODT featur ...